DESCRIPTION:

The disclosed invention describes a Smart Three Axis Compliant (STAC) interconnect designed to revolutionize ultra-thin chip-to-chip and chip-to-board high density 3D integration. STAC can also support super-fine pitch (20um pitch) batch processed integration at wafer level.

POTENTIAL APPLICATIONS:

All aspects of chip-to-chip and chip-to-board high density 3D integration packaging.

ADVANTAGES:

• STAC interconnect technology is three dimensionally compliant, with possible six degrees of freedom movement during operation.

• STAC interconnected chips can be batch processes via microfabrication techniques at the wafer-level.

• STAC interconnected chips should display improved performance, in more diverse applications, and with significant reductions in both production time and fabrication costs.

PATENT STATUS:

Initial internal disclosure documents filed, patent strategy is being evaluated.